MIT-6.175 Introduction/Contents

What is 6.175?

6.175 teaches the fundamental principles of computer architecture via implementation of different versions of pipelined machines with caches, branch predictors and virtual memory. Emphasis on writing and evaluating architectural descriptions that can be both simulated and synthesized into real hardware or run on FPGAs. The use and design of test benches. Weekly labs. Intended for students who want to apply computer science techniques to complex hardware design.

Topics include combinational circuits including adders and multipliers, multi-cycle and pipelined functional units, RISC Instruction Set Architectures (ISA), non-pipelined and multi-cycle processor architectures, 2- to 10-stage in-order pipelined architectures, processors with caches and hierarchical memory systems, TLBs and page faults, I/O interrupts.

Instructors

• Arvind
• Quan Nguyen (TA)

Lectures

MWF 3:00 pm, 34-302.

Lab Assignments Directory

• MIT-6.175 Introduction/Contents
• Lab 0: Getting Started
• Lab 1: Multiplexers and Adders
• Lab 2: Multipliers
• Lab 3: FFT Pipeline
• Lab 4: N-Element FIFOs
• Lab 5: RISC-V Introduction - Multi-cycle and Two-Stage Pipelines
• Lab 6: RISC-V Processor with 6-Stage Pipeline and Branch Prediction
• Lab 7: RISC-V Processor with DRAM and Caches
• Lab 8: RISC-V Processor with Exceptions

Project

• Part 1: Store Queue
• Part 2: Cache Coherence

Schedule

Please check back frequently as this schedule may change.

This calendar is also available on Google Calendar.

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